This application claims the priority of Korean Patent Application No. 2002-62571, filed on Oct. 14, 2002, in the Korean Intellectual Property Office, the contents of which are incorporated herein in their entirety by reference.
1. Field of the Invention
The present invention relates to a parameter generating circuit and a method of generating a parameter, and more particularly, to a parameter generating circuit for deciding a priority of master blocks in a system bus, the master blocks transmitting data through the system bus, and a method of generating a parameter for the same.
2. Description of the Related Art
As integrated systems in chips become larger, the number of master blocks included in the chips increases. Thus, there have been many studies on effective ways to occupy and connect a system bus.
A chip, in which a plurality of blocks are integrated, has various functions and is widely used in various fields. Accordingly, it is necessary to apply a different arbitration priority between blocks and master blocks in the chip according to the field of use.
Thus, a conventional arbitration scheme using a fixed priority has been developed such that a rotating priority and a round-robin priority are introduced. Recently, a programmable fixed priority, which allows a priority to be flexibly programmed according to each master block, has been suggested to provide an effective arbitration scheme suitable for an application field where master blocks are used.
However, in a chip to which the programmable fixed priority is applied, since an appropriate priority is decided by testing the chip through trial and error and there are various master blocks even in the chip specific for one field, data are transferred smoothly in a certain master block, but they are not smoothly transferred in another master block.
In this case, overall efficiency of the bus is reduced due to starvation in a specific master block though an appropriate priority is decided.
FIG. 1 is a block diagram of a general system-on-chip SOC.
Referring to FIG. 1, a general system-on-chip SOC 100 includes a plurality of master blocks 120 to 170 and a slave block 180. The SOC 100 further includes a system bus arbitrator 190 that arbitrates occupations of a system bus 110 between the master blocks 120 to 170.
In FIG. 1, a general direct memory access (GDMA) 150, a peripheral component interconnect (PCI) host 140, a universal serial bus (USB) host 170, an Ethernet media access control (Ethernet MAC) 120, a segmentation and reassembly (SAR) 160, and a central processing unit (CPU) 130 present the master blocks, and a memory controller 180 presents the slave block.
The master blocks 120 to 170 output a request signal, which indicates that the system bus 110 is needed for data transfer, to the system bus arbitrator 190. After the system bus arbitrator 190 completes the arbitration, the master blocks 120 to 170 obtain occupations of the system bus 110 upon receipt of a grant signal from the system bus arbitrator 190.
In general, since only one system bus 110 is included in the SOC 100, only one master block can occupy the system bus 110. If a plurality of master blocks 120 to 170 are connected to the system bus 110, each master block outputs the request signal in order to occupy the system bus 110, and the system arbitrator 190 outputs the grant signal according to a priority of the master blocks 120 to 170 to allow occupation of the system bus 110.
At this time, the master blocks, which are mainly used in the SOC 100, change according to an application field of the SOC 100, and the arbitration scheme of the system bus arbitrator 190 is important for effective occupations of the system bus 110 in each application field.
Therefore, the system bus arbitrator 190, which can program and control the priority or an occupation value of the system bus, will be effective for the system bus 110.
Although the system bus arbitrator 190 can program and control the priority or occupations of the system bus, the system bus 110 cannot effectively operate without the appropriate priority or the occupation value. The appropriate priority or the occupation value is obtained by trial and error in a real test, but still, it does not guarantee the effective operation of the system bus 110.
For example, when the SOC 110 of FIG. 1 is used in a home gateway, data transfer of the USB host 170 may increase, or data transfer of the USB host 170 may decrease and those of the PCI host 140 or the SAR 160 may increase at times.
Accordingly, although the SOC 100 is applied to one application field, the master block, which requests data transfer, may be different according to the data transfer environment. Therefore, a preset priority or occupation value programmed by the system bus arbitrator 190 cannot provide an optimal system bus environment when the data transfer environment is changed.